TSMC Shares 3nm Power and Performance Gains & Details For Potential 2nm Design

Dr. Y.J. Mii during his keynote at TSMC's 2021 Online Technology Symposium. Image: TSMC 2021 Online Technology Symposium/Taiwan Semiconductor Manufacturing Company

The Taiwan Semiconductor Manufacturing Company (TSMC) shared the latest details about its leading-edge manufacturing nodes today. TSMC's statements came at its 2021 Online Technology Symposium, which kicked off earlier today. At the outcome, TSMC's senior vice president of research and development, Dr. Yuh Jier Mii, shared details most the fab's latest semiconductor manufacturing processes, including its N6, N5, N4 and N3 process nodes. These include information most the processes' defect densities, yields and production timelines.

TSMC Outlines Stiff Customer Adoption For It N3 (3nm) Process Node – Expects New Record Outs To Be Double Over Predecessor

During his keynote, Dr. Mii started by highlighting that in 2020, TSMC increased its research and development spending and headcount to stand at record levels. He also outlined that since the fab first introduced its 7nm process in 2018, information technology has shipped more than than one billion chips manufactured past it. The 7nm node has proven crucial for chip designer Advanced Micro Devices, Inc (AMD), whose central processing units (CPUs) and graphics processing units (GPUs) were among the first to use the manufacturing technology. This enabled the company to increment its marketplace share confronting the larger Intel Corporation and bring its products at a level with the larger visitor over time.

Commenting on TSMC's N6 process node, Dr. Mii outlined that this process improves logic density past 18% over its N7 (7nm) process and uses more layers with farthermost ultraviolet lithography (EUV) during the production process. He too stated that the N6 node would account for roughly half of TSMC's N7 output by the terminate of this year, as products using the procedure are in high-volume production. Fifty-fifty though the process volition print finer circuits compared to N7, Dr. Mii besides confirmed that the defect density for N6 equals N7 and that EUV usage enables TSMC to reduce manufacturing time.

Lower manufacturing time is a crucial achievement for TSMC, equally the fab saw this time duration increase equally it introduced the 10nm and 7nm process nodes after the 14nm and 16nm nodes. While the N6 process improves density and manufacturing over the N7, it is still classified as the latter'due south 'sub-process' due to similar design rules.

Dr. Mii highlighted during TSMC's applied science symposium that the N3 (3nm) process has received stiff industry back up and improves performance over the fab's first generation 5nm procedure. Epitome: TSMC 2021 Online Applied science Symposium/Taiwan Semiconductor Manufacturing Company

Delving deeper into TSMC'southward progress with the N3 process node, Dr. Mii stated that 3nm would meliorate power consumption or operation over the first generation of its N5 family. The offset generation N5 node is TSMC'southward 5nm process, which has already entered mass production. This procedure is followed by N4, which, compared to N5, offers a vi% smaller fleck die, improves ability consumption and performance and uses fewer masks during the production process. The usage of fewer masks hints that perhaps TSMC will increase EUV adoption with the newer process, and the executive also stated that N4 risk production will start in the third quarter of this year.

In an important disclosure, Dr. Mii stated that the N3 process has witnessed more than twice the tape-outs during its commencement yr compared to the N5. A record-out in the semiconductor industry refers to chip designers finalizing their designs before sending them over to a fab, which then either finetunes the design or moves towards production.

TSMC'due south SVP R&D Dr. Y.J. Mii outlined at its latest applied science conference that it has managed to reduce voltage variation with its new nanosheet transistors. Image: TSMC 2021 Online Engineering science Symposium/Taiwan Semiconductor Manufacturing Company

While non explicitly tying TSMC's piece of work on nanosheet transistors with its 2nm procedure, Dr. Mii shared key details for the circuits that might end upwardly representing his company's near meaning manufacturing jump in years. He outlined that nanosheet transistors accept managed to implement tighter threshold voltage (Vt) command. In semiconductor design, Vt refers to the minimum voltage needed for a circuit to work, and even the slightest variations can innovate blueprint constraints and functioning drops.

According to the executive, the nanosheet transistors accept managed to "demonstrate nanosheet transistors with more than 15% lower Vt variations equally shown in blueish compared to that of a very good FinFET transistor equally shown in red."

He proceeded to highlight his company's research with carbon nanotube transistors. TSMC's chairman, Dr. Mark Liu, focused on these transistors earlier this year at the ISSC 2021 conference, where he highlighted new material development as a key quantum in the area.